1. Field of the Invention
The embodiments of the invention generally relate to routed wiring design, and, more particularly, to a routed wiring design with minimized correlated coupling between nets and an associated method of reducing correlated coupling between nets.
2. Description of the Related Art
Coupling capacitance occurs between parallel nets. This coupling causes crosstalk noise, which in turn can cause signal delays and circuit failure. Specifically, if the switching window of parallel adjacent nets overlap one net may act as an aggressor net impacting the switching time (i.e., the time when an output transition from low to high voltage or high to low voltage occurs) and/or the slew rate (i.e., the rate of change of output from low to high voltage or high to low voltage) of the adjacent net (i.e., the victim net). For example, when aggressor and victim nets switch at overlapping times, but in opposite directions (i.e., low to high or high to low) and/or at different slew rates, the slew rate of the victim net can be increased or decreased and the switching time of the victim net can occur earlier or later. Increasing the slew rate or causing the switching time of the victim net to occur later can cause setup time violations (e.g., at flip-flops or latches) or output timing window errors. Decreasing the slew rate or causing the switching time of the victim net to occur earlier can cause hold time violation.
One technique that has been used to avoid coupled noise induced timing fails is to move wires apart and in this way to reduce the coupling capacitance. This method does not work well in highly congested chip areas, were there is no additional space for the enlarged isolator distance. Other methods common are the creation of more timing margin by using stronger drivers. In critical nets this method is already exhausted. Therefore, there remains a need in the art for a method that re-routes an array to minimize correlated coupling between nets in congested wiring areas with minimal upset of the current design.